1.
a) and b)  
Instruction at OF stage will be forward to Result register and nop 
be output to IR between OF adn ALU.
    
             NOP o-------------    OF stage
              _|_|_            |
              \1_0/---------   |
        ________|_______   |   |
       |>______IR_______|  |   |
          ______|__________|___|______
         |                 |   |      |  ALU/MEM stage
         |                 |   |  ... |
         |                 |  _|_|_   |
         |           ...---o--\1_0/   |
         |______________________|_____|
                |               |
        ________|_______ _______|_______
       |>______IR_______|______result______|
                |
c) If OF has a buble, ALU block itself and wait.
   If OF is blocked by itself then unblock it and forward the instruction
   to result register.

2
Assuem if both pipeline a and pipeline b want to write to the same register at RS
stage, data in pipeline a will be discasted and data in pipeline b will be written to that register.
The same assumption is made when a and b want to write to same memory address at ALU/MEM stage.

OF/AC.IRa.need_r1 && ALU.IRa.write_register && OF.IRa.r1 = ALU.IRa.r1
OF/AC.IRa.need_r2 && ALU.IRa.write_register && OF.IRa.r2 = ALU.IRa.r
OF/AC.IRa.need_r1 && RS.IRa.write_register && OF.IRa.r1 = RS.IRa.r1
OF/AC.IRa.need_r2 && RS.IRa.write_register && OF.IRa.r2 = RS.IRa.r1

OF/AC.IRa.need_r1 && ALU.IRb.write_register && OF.IRa.r1 = ALU.IRb.r1
OF/AC.IRa.need_r2 && ALU.IRb.write_register && OF.IRa.r2 = ALU.IRb.r
OF/AC.IRa.need_r1 && RS.IRb.write_register && OF.IRa.r1 = RS.IRb.r1
OF/AC.IRa.need_r2 && RS.IRb.write_register && OF.IRa.r2 = RS.IRb.r1

block IF and OF stages of pipeline a and pipeline b during the next clock cycle.



OF/AC.IRb.need_r1 && ALU.IRb.write_register && OF.IRb.r1 = ALU.IRb.r1
OF/AC.IRb.need_r2 && ALU.IRb.write_register && OF.IRb.r2 = ALU.IRb.r
OF/AC.IRb.need_r1 && RS.IRb.write_register && OF.IRb.r1 = RS.IRb.r1
OF/AC.IRb.need_r2 && RS.IRb.write_register && OF.IRb.r2 = RS.IRb.r1

OF/AC.IRb.need_r1 && ALU.IRa.write_register && OF.IRb.r1 = ALU.IRa.r1
OF/AC.IRb.need_r2 && ALU.IRa.write_register && OF.IRb.r2 = ALU.IRa.r
OF/AC.IRb.need_r1 && RS.IRa.write_register && OF.IRb.r1 = RS.IRa.r1
OF/AC.IRb.need_r2 && RS.IRa.write_register && OF.IRb.r2 = RS.IRa.r1

OF/AC.IRb.need_r1 && OF/AC.IRa.write_register && OF.IRb.r1 = OF/AC.IRa.r1
OF/AC.IRb.need_r2 && OF/AC.IRa.write_register && OF.IRb.r2 = OF/AC.IRa.r1

ALU.IRb.read_mem && ALU.IRa.write_mem && ALU.IRb.ea = ALU.IRa.ea

lock IF and OF stages of pipeline a during the next clock cycle.