Assignment 11, due April 16

Part of the homework for 22C:122/55:132, Spring 2004
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due on Fridays at the start of class, and unless there is what insurance companies call "an act of God", the only exceptions to this rule will be by advance arrangement.

  1. Consider the example architecture from the exam. Believe it or not, this architecture actually has some instructions that are almost variable in length. Specifically, consider this instruction:
        01 0000 0000 000000  load R0 R0 0
        xxxxxxxxxxxxxxxx     X
    This loads the 16-bit value X into the program counter; it will probably be a common form of unconditional branch, and making it faster will therefore be worthwhile.

    a) Document the changes to the ALU/MEM pipeline stage that are required to use pipeline-stage promotion to do this.

    b) Load-immediate could be coded as, for example

        01 0101 0000 000000  load R5 R0 0
        xxxxxxxxxxxxxxxx     X

    This loads the 16-bit constant X into R5, but then, the very next instruction is is same constant X! What additional logic do you need to add to your solution for parts a) and b) to make the machine automatically skip the constant X when R0 with a displacement of 0 is used as an operand on the load instruction. (Hint, this is remarkably easy if you make the right assumptions about what is already solved by the ALU stage!)

    c) The promoted value will come from IR input to the OF/EA stage. What do you do if that stage contains a bubble or is blocked? (Assume you have solved both parts A and B first. The bubble could be there because the IF stage couldn't get anything new from memory in time for this pipeline cycle, and the instruction X can itself be blocked in the OF/EA stage.)

  2. Suppose we build a 2-way superscalar version of our example machine, so it fetches 32 bits of instruction stream per clock cycle, and it has two pipes, a, for the first instruciton in the longword, and b, for the second instruction. Use the following naming conventions for fields of interstage registers: OF/AC.IRa.op is the opcode of the IR in pipeline a used as input to the OF/AC pipeline stage. List all of the interlock conditions that must be checked in order to determine if the OF/AC stages should block. (There will be two sets of conditions, one for pipeline a and one for pipeline b.)