Assignment 10, due April 9

Part of the homework for 22C:122/55:132, Spring 2004
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due on Fridays at the start of class, and unless there is what insurance companies call "an act of God", the only exceptions to this rule will be by advance arrangement.

  1. Consider the example architecture given in the midterm study questions and the subject of much of the midterm exam, not to mention the last homework assignment, with this 4-stage pipeline:
    1. IF -- instruction fetch
    2. OF/AC -- operand fetch (from registers) and address computation
    3. ALU/MEM -- arithmetic (operate) or memory reference (load/store)
    4. RS -- result store (to registers)
    Assume no result forwarding or other sophisticated tricks, and identify all of the interlock conditions for this processor, except that involved with self-modifying code. For each interlock condition, identify the Boolean condition that triggers the interlock and the pipeline stages that must stall when this interlock condition is true.

  2. Identify each of the possible forwarding paths in this architecture, and for each, indicate the Boolean condition that enables the path. (Note, these will correspond closely to a subset of the stall conditions identified in the first problem).