1. Ignore skip instructions and the fact that R0 is PC.


Instruction Fetch Stage
                                       True -----> need memory
                                     
         ---------o------------------------------> address to memory
        |       __|__               -------------< data from memory
        |      | +1  |             |
        |      |__ __|             |
        |         |                |
        |      ...|...             |
        |         |                |
        |  _______|_______  _______|___________________
        | |       pc      || op|r1|r2|  dd   |op'|sk|st| 
        | |_______________||___|__|__|_______|___|__|__|
        |_________|



Operand fetch stage:

 _______________            ____________________
|       pc      |          | op|r1|r2|  dd  |op'| 
|_______________|          |___|__|__|______|___|
       |                     |  |  |    |     |
       |     ----------------   |  |    |     | 
       |    |   ----------------o  o----|--------------------------> register number
       |    |  |                |       |     |      ---------------< data from registers
       |    |  |          ------|-------|-----      |             
       |    |  |         |      |        ---------  |                
       |    |  |         |      |                 | |             
       |    |  |         |      o---------------------------------->register number             
       |    |  |         |                        | |             
       |    |  |         |             -------------------------------<data frome registers  
       |    |  |         |            |           |_|__            
       |    |  |         |            |          |  +  |           
       |    |  |         |            |          |_____|           
  _____|_  _|__|_________|_   ________|______    ___|______
 | pc    || op|r1|r2|dd|op'| |       opa(r1) |  |   ea     |
 |_______||___|__|__|__|___| |_______________|  |__________|



ALU/memory stage:

                ______     __     ____________           __________
               | op|r1|   |op'|  |    opa(r1) |         |   ea     |
               |___|__|   |___|  |____________|         |__________|
                 |  |       |        |                       |            
write to memory  |  |       |        |        ---------------o------->address to memory                |         
   <-----|=2|----o  |       |        |       |               |
data to memory<--|--|-------|--------o-------|-------------- |
                 |  |  __  _|_       |       |              ||
                 o--|-|=0|-\ /       |       |              ||
                 |  | |__|  |        |       |    _____   __||___
                 |  |        --------|-------|---|aluop|-|  alu  |
                 |  |         ____   |       |   |_____| |_______|
                 |  |        |    |  |       |               |              
                 o--|--------| =1 |--|-------|---------------|-------> needs memory
                 |  |        |____|  |       |               |        
                 |  |                |       |      ---------       
                 |  |                 -------|-    |                   
                 |  |                        | |  -|-----------------<  data from memory            
                 |  |          --------------o | | |
                 |  |         |             _|_|_|_|_             
                 |  |         |            | 3 2 1 0 |                 
                 o--|---------|------------|         |                          
                 |  |         |            |_________|
                _|__|_  ______|________  _______|_______
               | op|r1||       ea      ||     result    |
               |___|__||_______________||_______________|


Operand-store stage:
    __     _____                   _______________
   |st|   | op|r|                 |     result    |
   |__|   |___|_|                 |_______________|
     |  __  |  |                          |
     |-|=0|-o   --------------------------|-------> register number       
    _||     |                ________     o-------> data to registers 
   |and|    |               |  = 1   |    ___                         
   |___|    o---------------|  or    |---|   |--------> write register
     |                      |__=_3___|   |or |                     
     |                                   |   |             
      -----------------------------------|___|         


2.Based on the structure that read and write memory at the ALU/memory stage
a)two delay slots.
  
b)zero delay slot.
 
c)three delay slots.
 
d) 
 1) Modify the immediately following word.
    For slots < 2, D is not executed.
    For slots >=2, D is executed.

 2) Modify the word following the next instruction.
    For slots < 1, D is not executed.
    For slots >=1, D is executed.

Based on the structure that read and write memory at the OS stage
a)two delay slots.  
     
b)one delay slot.
 
c)three delay slots.
 
d) 
 1) Modify the immediately following word.
    For slots < 3, D is not executed.
    For slots >=3, D is executed.

 2) Modify the word following the next instruction.
    For slots < 2, D is not executed.
    For slots >=2, D is executed.