Assignment 9, due April 5

Part of the homework for 22C:122/55:132, Spring 2004
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due on Fridays at the start of class, and unless there is what insurance companies call "an act of God", the only exceptions to this rule will be by advance arrangement.

  1. Consider the example architecture given in the midterm study questions and the subject of much of the midterm exam. Apply the methodology of the end of lecture 26 to this architecture, assuming a 4-stage pipe with instruction-fetch, operand-fetch, ALU/memory and operand-store stages. The ALU/memory stage does all operand memory references, while the operand-fetch stage gets operands from the instruction register and general purpose registers, and the operand store stage puts results in general purpose registers. Ignore, for the moment, skip instructions and the complexities introduced by the fact that register zero is the program counter.

  2. How many delay slots does this processor have for:

    a) register operands?

    b) memory operands?

    c) branches (assume R0 is the PC and is not handled specially).

    d) self modifying code.

    For the last, consider the case where an instruction stores the data D in the immediately following word. Does D get executed (no delay slots), or does the previous value of that word get executed (one or more delay slots)? If the latter, consider the case where an instruction stores the data D in the word following the next instruction. Does D get executed (no more than one delay slot) or does the previous value get executed (at least two delay slots)?