1.

5000  load R1 R0 10    ;load 0 to R1
5001  load R2 R0 10    ;load the starting address of the array to R2
5002  load R3 R0 10    ;load the address of the array size to R3
5003  load R3 R3 0    ;load the array size to R3
5004  R3 R2 add no-skip store     ;R3 is address just above the top of the array
5005  op R2 R3 sub skip-if<0 no-store    ;check if all the items have been added
5006  load R0 R0 7    ; if true, load address 201F to pc
5007  load R5 R2 0    ; otherwise load the item to R5
5008  op R1 R5 add no-skip store    ; add that item to R1 
5009  load address R2 R2 1     ;increment R2 to point to the next item 
5010  load address R0 R0 -6    ;jump back to 5005
5011  0          ;constant 0
5012  7FE6       ;array address
5013  6A07       ;array size address
5014  201F       ;address jump to

2.
a)Register transfer diagram for division

        Data    ======o=====o======o======o======o======o==
	Address ======|=====|======|======|======|======|==
	Read    ------|-----|------|------|------|------|--
	Write   ------|-----|------|------|------|------|--
                      |     |      |      |      |      |     
            rier ...  |  --/_\     |   --/_\    n/   --/_\    
            racc     n/     |     n/  ____|______|______|_____
            rica      |     |      | |    |      |  ____|___  |
                      |     /n    _|_|_   /n    _|_|_   |   | |
            run  ...  |     |   --\0_1/   |   --\0_1/   /n  | |
                   ___|___  |    ___|___  |    ___|___  |   | |
	    cier -|>_icand| |  -|>_acc__| |  -|>_ier__| |   | |
            cacc      |     |       |     |       |     |   | |
            cica       -----o       o-----        o-----    | |
                            |      _|_____________|_        | |
                            |     |______<<1________|       | |
                            |       |             |         | |
                            |    ---o        -----o         | |
                         ___|___|__ |      __|__  |         | |
                        |   b   a  ||     |_+1__| |         | |
                        | >=0 a-b  ||        |    |         | | 
                        |__________||        |    |         | |           
                           |  |     |       _|____|__       | |
                           o--|-----|-------\1_____0/       | |
                           | _|_____|_            |        n/ /n
                           *-\1_____0/            |         | |
                                 |                |_________| |
                                 |____________________________|


b) Register transfer diagram. One bit control input is stored in fun regster.
   Assume: when fun=0, perform multiplication and when fun=1 perform division. 

        Data    ======o=====o======o======o======o======o=============o=====o=
	Address ======|=====|======|======|======|======|=============|=====|=
	Read    ------|-----|------|------|------|------|-------------|-----|-
	Write   ------|-----|------|------|------|------|-------------|-----|-
                      |     |      |      |      |      |             |     |
            rier ...  |  --/_\     |   --/_\    n/   --/_\            |  --/_\
            racc     n/     |     n/  ____|______|______|_____       n/     |
            rica      |     |      | |    |      |  ____|___  |       |     |
            xx        |     /n    _|_|_   /n    _|_|_   |   | |       |     |
            run  ...  |     |   --\0_1/   |   --\0_1/   /n  | |       |     |
                   ___|___  |    ___|___  |    ___|___  |   | |    ___|___  |
	    cier -|>_icand| |  -|>_acc__| |  -|>_ier__| |   | |  -|>_fun__| | 
            cacc      |     |       |     |       |     |   | |       |     |
            cica    --|-----|-------o-----        o---o-    | |       *-----o  
            select  | |     |      _|_____________|_  |     | |              |
                    | o-----|     |______<<1________| |    n/ /n             |
                    | |     |       |             |   |     | |              |
                    | |     |    ---         -----o   |     | |              | 
                    | |  ___|___|__ |      __|__  |   |     | |              |
                    | | |   b   a  ||     |_+1__| |   |     | |              |
                    | | | >=0 a-b  ||        |    |   |     | |______________|______
                    | | |__________||        |    |   |     |_________       |      | 
                    | |    |  |     |       _|____|__ |            ___|___   |   ___|___  
                    | |    o--|-----|-------\1_____0/ |           /1_____0\--o--/1_____0\
                    | |    | _|_____|_            |   |            |     |       |     | 
                    | |    *-\1_____0/            |   |            |     |       |     | 
                    | |          |                |___|____________|     |       |     |
                    | |          |____________________|__________________|_______|     |            
                    |_|_________________              |                  |             |
                      |                 |             |                  |             |
                      |_________        |             |         ---------*             |
                                |      _|_____________|_        |                      |
                                |     |______>>1________|-      | ---------------------*
                                |       |             |   |     | |
                                |    ---o             |   |     | |
                               _|___|_  |             |   |     | |
                              |___+___| |             |   |     | |
                                 _|_____|_            |   |    n/ /n
                                 \1_____0/--<---------|---*     | |
                                     |                |_________| |
                                     |____________________________|
  


c) The change to the bus interface is:
   using the start signal as the select signal to clock the fun register.

                                ...
                                ...
                                    ___  
                         |-|-|-----| 4 |--- cica     ___          \
           to and from    -|-|-----| x |------------|2 x|-- cacc   clock the
           coprocessor      -|-----|AND|------------|OR_|-- cier   register
          control unit        -----|___|--            |           /
                                          |           |
              start-----------<-----------o---select  |
                                                      |
              step ------------------------>----------*
              run  ------------------------>------------ run
  

d)
Mealy machine:
              input: start
             output: step, run
             n states.


           -<--     --->---     --->---    --->---       ...
         / 0/00 \ /  1/11   \ /  -/11  \ /  -/11   \ /   ...   \
        (       (1)         (2)        (3)         (4)         (n) 
         \      / \                                            /
           ----     ---<--------------------------------------  
                               -/11