Assignment 5, due Feb 20

Part of the homework for 22C:122/55:132, Spring 2004
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due on Fridays at the start of class, and unless there is what insurance companies call "an act of God", the only exceptions to this rule will be by advance arrangement.

  1. The first step in evaluating a computer architecture is to evaluate whether it is, in fact, a general purpose machine. For a Von Neumann architecture, this means verifying that its memory addressing is sufficiently general to allow all possible data and control structures to be exploited.

    Consider the Ultimate RISC, with a the 8-function ALU documented in the notes, for example; direct addressing on this machine is the only obvious addressing mode, but languages like C demand far more; show how each of the following can be done in this horrible little instruction set:

    a) Given the variable p, holding a pointer, you must be able to load or store the value of *p, the variable pointed to by that pointer.

    b) Given that the variable a holds the address of word zero of an array of integers, and the variable i holds an one-word item, compute the address of the array element a[i].

    c) Given that the variable s holds the address of a structure in memory, and that the constant f is the displacement of a field from the start of that structure, compute the address of the field s->f (which, in C, can also be written as (*s).f).

  2. Consider the possibility of using the same 8-function ALU that was suggested for the Ultimate RISC as an ALU in the Minimal CISC. This takes a 3-bit function select code, so we could use the minimal CISC opcode 110 (currently subtract) as the prefix on a 3-bit ALU function-select syllable. In this case, the minimal CISC instruction set now has 7 instructions that are 3 bits each and one instruction that is 6 bits.

    a) Looking at the program-style description of the fetch-execute cycle, evaluate two alternatives: First, the 6-bit instruction is forbidden to cross word boundaries, and second, we allow the 2 3-bit syllables of the 6-bit instruction to span word boundaries. Which alternative would you prefer to implement? Justify your answer.

    b) Give the program-level description for your preferred solution.

    c) Give the register-transfer component level design for your preferred solution.

    d) Give the control unit microcode for your preferred solution, with sufficient documentation that it can be understood in terms of parts b and c.