Assignment 4, due Feb 13

Part of the homework for 22C:122/55:132, Spring 2004
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due on Fridays at the start of class, and unless there is what insurance companies call "an act of God", the only exceptions to this rule will be by advance arrangement.

  1. Look at the GCD engine from the lecture on Feb 4. The data part of that design involved the use of two different subtractors, one to compute A-B and the other to compute B-A. Consider using a single with a carry input that has conditional inverters on both inputs (so it can compute any of several functions, including A+(~B)+1 or (~A)+B+1 but also including A+B and many others. The adder also has a carry output and an output indicating that the result was entirely zero.

    a) Redo the GCD engine register-transfer logic in terms of this single arithmetic unit.

    b) Work out the control unit (as a Moore machine) for this new system. It should still compute the same algorithm! (You may find that the state count changes! Then again, it may not! The reason I don't know is that the new arithmetic unit doesn't necessarily offer the same comparison flexibility as the old one.)

  2. We made no use of busses in the design given above or the design given in the notes. This problem is not necessarily one that lends itself to large scale use of busses, but consider replacing the two multiplexors with a single bus. This bus takes, as sources of data, the inputs from the outside world and the data from the arithmetic unit used in the first problem. The data on the bus can be directed to either the A or B registers.

    a) Redo the GCD engine register-transfer logic in terms of this single bus.

    b) Work out the control unit. It definitely takes an extra state becaus3e you have to sample the inputs on different bus cycles!

  3. How would you access an element of an array on the IAS machine? This involves self-modifying code! Give the instructions needed, in terms of the instruction set documented in the notes for the IAS machine.