1.
dividend.

2.
Register transfers in the sets:
{C,D,E,F}
{H,I}
can be carried out in parallel.

3.


  input_B   divisor      
              |     |--------|
     |       _|_____|_       |
     |      | x     y |      |
     |      |   x-y   |      |
     |      |_c_______|      |
     |        |    |         |
y>=x |  ___   |    |         |
<----)-|not|--|    |         | 
     | |---|       |         | 
     |	 	   |         |
     |----|	   |         |
     	  |   |----|         |
F_dividend|   |              |
        __|___|__            |
    ____\ 0   1 /            |
	 \_____/             |
	    |                |
        ____|_____           |
    ___|dividend  |          | 
       |__________|          | 
C_dividend  |                |
	    |________________|
	    |
	    |


4.
control input: input_ready.
               y>=x, y--dividend,x--divisior

5.
Register clock signal: C_output_valid (C1), C_dividend (C2), C_quotient (C3),
Functional element control signals: F_output_valid (F1), F_dividend (F2), F_quotient (F3).
    

6.


   courrent state   IR   y>=x   next state
         1          0      -       1
	 1          1      -       2
	 2          -      1       3
	 2          -      0       4
         3          -      1       3
	 3          -      0       4
	 4          -      -       1
_______________________________________________________________________

    state   C1   F1   C2   F2   C3   F3
     1      0    -    0    -    0    -
     2      1    0    1    0    1    0
     3      0    -    1    1    1    1
     4      1    1    0    -    0    -