1.

A  B  C  C' S
00 00 0  0  00
00 00 1  0  01
00 01 0  0  01
00 01 1  0  10
00 10 0  0  10
00 10 1  0  11
00 11 0  0  11
00 11 1  1  00

01 00 0  0  01
01 00 1  0  10
01 01 0  0  10
01 01 1  0  11
01 10 0  0  11
01 10 1  1  00
01 11 0  1  00
01 11 1  1  01

10 00 0  0  10
10 00 1  0  11
10 01 0  0  11
10 01 1  1  00
10 10 0  1  00
10 10 1  1  01
10 11 0  1  01
10 11 1  1  10

11 00 0  0  11
11 00 1  1  00
11 01 0  1  00
11 01 1  1  01
11 10 0  1  01
11 10 1  1  10
11 11 0  1  10
11 11 1  1  11

2.
input NOT gates : 5
row NAND gates: 32
output NAND gate: 3

3.
a)
                 _______________________
 		|	_______        |
		|      |       |       |
	 	|------|D     Q|----   |
		       |  _    |       |
	       ___     |   |_  |       |
    input  ___|   \    |      _|       |
           ___|    )---|>C    Q|-------|
    clock     |___/    |_______|
								       

														     
            ___________________________
      	   |	____      _______     |
	   |---\\   \    |       |    |
                ))   )---|D     Q|----+---
    input  ----//___/    |  _    |
                         |   |_  |
                         |      _| 
             clock------ |>C    Q|-----
                         |_______|


b)
 
 If the control input changes from 1 to 0 when the clock is high, the c input will go low. It will cause 
 the circuit to toggle, which is supposed not to happen.


4.

Mealy:

  input  current  next  output
         state    state
   0      A         A     0
   1      A         B     0 
   0      B         B     1
   1      B         A     1
   

Moore:

  input  current  next       state  output
         state    stat        A         0
   0      A        A	      B         1 
   1      A        B
   0      B        B
   1      B        A