10. Hawk Two Register Instructions
Part of
the Hawk Manual

10.1. Two Register Format
10.2. Bitwise Logical Operations
10.3. Extended Precision Arithmetic
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0 0 0 1  dst       src 
The two register arithmetic format instructions are 16 bits each, specifying one source register and one destination register. All is combine the source with the value formerly in the destination register.
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0 0 0 1  dst (nz)  1 0 1 1  src (nz)  AND  dst,src  r[dst] =(r[dst] ∧ r[src])  
0 0 0 1  dst (nz)  1 0 1 0  src (nz)  OR  dst,src  r[dst] =(r[dst] ∨ r[src])  
0 0 0 1  dst (xz)  1 0 0 1  src (0)  EQU  dst,src  r[dst] =(r[dst] ≡ r[src]) 
AND OR EQU  N = r[dst]:31  — result is negative  
Z = (r[dst] = 0)  — result is zero  
V = C = 0  
The AND, OR and EQU (equivalent) operations combine each bit of the source register with the corresponding bit of the destination register using the indicated boolean operation.
Thus, with the AND operation, bits will be set in the destination register only if they were already set there and the corresponding bits were already set in the source register. With the OR operation, each bit of the destination will be set if that bit was set in either the source, the destination or both.
The EQU operation asks if the bits of the source and destination registers were equivalent. Bits are set in the destination register only when the source and destination bits were the same. Formally, this is the same as the not exclusive or of the source and destination, so (a≡b) = ~(a⊕b)
Because ~x (not x) is the same as x≡0 (comparing the bits of x with zero), assemblers should provide a NOT operation that is the same as EQU with src=0.
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0 0 0 1  dst (nz)  1 0 0 1 0 0 0 0  NOT  dst  r[dst] = ~r[dst] 
Because a⊕b (a exclusiveor b) is the same as a≡~b (a equivalence to not b), the exclusiveor of two operands can be computed using a combination of NOT and EQUIV. For example, the following sequence exclusiveors R4 with R3:
EQUIV R3,R4 NOT R3
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0 0 0 1  dst (x)  0 1 1 1  src (0)  ADDC  dst,src  r[dst]=r[dst]+r[src]+C  
0 0 0 1  dst (x)  0 1 1 0  src (0)  SUBB  dst,src  r[dst]=r[dst]r[src]~C 
ADDC  N = r[dst]:31  — result is negative  
Z = (r[dst] = 0) ∧ Z  — result is zero  
V = (( r[dst]:31 ⊕ r[dst]':31 ) ∧ ( r[dst]':31 ≡ r[src]':31 ))  
C = carry out of adder  
SUBB  N = r[dst]:31  
Z = (r[dst] = 0) ∧ Z  
V = (( r[dst]:31 ⊕ r[dst]':31 ) ∧ ( r[dst]':31 ⊕ r[src]':31 ))  
C = not borrow from difference  
The ADDC (add with carry) and SUBB (subtract with borrow) instructions are used to perform integer arithmetic on quantities longer than 32 bits. These add or subtract one register from another taking into account the carry or borrow bit left over from the addition or subtraction of the less significant bits.
The condition codes reflect the extended precision result. N is set if the result is negative, Z is set if the entire result is zero; that is, it is reset if the result was nonzero, and it remains set only if the result was zero and it was already set. V is set if two's complement overflow occurred, and C is set if there was a carry out of the most significant bit (equivalent to no borrow out of the most significant bit).
The following sequence does a 64 bit add of R5R6 to R3R4, assuming that the least significant 32 bits are in the lower numbered register:
ADD R3,R3,R5 ; add low half ADDC R4,R6 ; add high half
The following sequence rotates the 32 bit value in R1 1 bit left, so the old value of the sign bit goes into the least significant bit:
ADDSL R3,0,1 ; shift 1 bit left ADDC R3,0 ; bring carry around
The ADDC instruction alone, with src=dst, rotates the 33 bit value composed of the source register concatenated with the condition code register 1 bit left. This is useful for leftshifting multiword quantities. Assemblers should support this as with the mnemonic ROL.
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0 0 0 1  dst (x)  0 1 1 1  src=dst  ROL  dst  r[dst]= r[dst]«1+C 