# 7. Hawk Byte and Halfword Instructions

## 7.1. Byte and Halfword Format

 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 0 1 - - dst s1 s2

Byte and halfword manipulation instructions are 16 bits each, and operate register to register. The destination register R[dst] is changed using data from the first source register R[s1], while the least significant bits of the second source register, R[s2] control the which byte or halfword is selected.

Where LOADS and STORES ignore the least significant 2 bits of the address, using the most significant 30 bits to select a word in memory, these instructions use only the 2 least significant bits to select a byte or halfword within a word. Byte selection involves a field running from bits b+7 to b of a register, while halfword selection involves a field running from bits h+15 to h of a register:

b = r[s2]∧3 * 8   — low bit of byte

h = r[s2]∧2 * 8   — low bit of halfword

## 7.2. Byte and Halfword Stuffing

 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 0 1 1 1 dst (nz) s1 (0) s2 (0) STUFFB dst,s1,s2 r[dst]:b+7:b = r[s1] 0 1 1 0 dst (nz) s1 (0) s2 (0) STUFFH dst,s1,s2 r[dst]:h+15:h = r[s1]

 STUFFB   STUFFH NZVC unchanged

STUFFB and STUFFH stuff the low byte or the low halfword halfword of r[s1] into the byte or halfword of r[dst] selected by the low 2 bits of r[s2], with no effect on the condition codes or the rest of r[s2].

In combination with LOADS and STORES, these operations are used store bytes or halfwords in memory. For example, if R3 holds a character and R4 is a pointer to a byte in memory, this instruction sequence will store that character in that byte, using R1 as a temporary register:

```	LOADS  R1,R4
STUFFB R1,R3,R4
STORES R1,R4
```

This idea comes from the DEC Alpha processor. On 32 bit machines with single store byte instructions, the CPU may have to perform all of the computations that are made explicit in the above instruction sequence.

## 7.3. Byte and Halfword Extraction

 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 0 1 0 1 dst (x) s1 (nz) s2 (0) EXTB dst,s1,s2 r[dst] = r[s1]:b+7:b 0 1 0 0 dst (x) s1 (nz) s2 (0) EXTH dst,s1,s2 r[dst] = r[s1]:h+15:h

 EXTB     EXTH N = 0 Z = (r[dst] = 0) — result is zero V = C = 0

The extract instructions take use the least significant two bits of r[s2] to select a byte or halfword from r[s1] and store that byte or word in the least significant byte or halfword of r[dst], clearing all other bits. This idea comes from the DEC Alpha architecture.

The extract operations set the Z condition code to report whether the result was zero. The other condition codes are all cleared.

These operations are used to load unsigned bytes and halfwords from memory. For example, if R4 is a pointer to a byte in memory, this instruction sequence will load a character from that byte into R3, using R1 as a temporary register:

```        LOADS  R1,R4
EXTB   R3,R1,R4
```

When R0 is given as s2, this specifies the constant zero, which is to say, byte or halfword zero. As a result, EXTB and EXTH may be used to combine the functions of a move and a truncate operation. For example, to extract the low byte of R3 and move it to R4, use:

```        EXTB    R4,R3,R0
```

Instead of using a two instruction sequence:

```        MOVE    R4,R3
TRUNC   R4,8
```

To test if a byte or halfword is zero, without changing any registers, extract it into R0. For example, to test if the low halfword of R3 is zero, use:

```        EXTH    R0,R3,R0
```