The Hawk Computer Architecture

Part of the Computer Architecture Pages
See also the Assembly Language Programming Pages
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Contents

  1. Overview
  2. Short Memory Reference Instructions
  3. Memory Reference Instructions
  4. Long Immediate Instructions
  5. Short Immediate Instructions
  6. Shift Instructions
  7. Byte and Halfword Instructions
  8. Add and Subtract Instructions
  9. Short Constant Instructions
  10. Two Register Instructions
  11. Special Instructions
  12. Branch Instructions
  13. Trap and Interrupt Service
  14. Support for Multiply and Divide
  15. The Floating-Point Coprocessor
  16. The Sparrowhawk Subset
  1. Emulator and Debugger Reference
  2. Emulated Devices
  3. Instruction Set Summary and Index
The assembly language source code used here can be assembled with the 32-bit machine independent SMAL assembler (version B); the opcodes for the Hawk are defined in a header file, hawk.h, that must be included at the head of each Hawk assembly language program. A Hawk emulator written in C runs under Linus and other versions of UNIX. There is a hello world program to demonstrate the Hawk.

Abstract

The Hawk computer is a fictional machine that incorporates many features of modern RISC processors without slavish adherance to any particular real machine. The Hawk instruction set is based on a 32 bit word, typical for modern machines, and includes 15 general registers, a modest number by modern standards.

Acknowledgement

The Hawk architecture began as a midterm exam question in my spring 1996 offering of Advanced Computer Architecture (22C:122) at the University of Iowa. That unnamed architecture grew into the Hawk through followup questions and discussions. I first reduced the Hawk to workable form for the fall 1996 offering of Computer Organization and Assembly Language Programming (22c:18); I owe quite a bit to my students in that and later classes for their patience in working bugs out of the emulator.

Original release: Mar. 6, 1996
Revised: Feb. 27, 2002 — BCDGET instruction replaced by EX3ADJ
Revised: Mar. 13, 2002 — SSQADJ, BTRUNC instructions added
Revised: July 25, 2002 — recode 0000, FFFF as no-ops, add ADJUST, MOVESL
Revised: Aug 1, 2008 — recode to reverse byte order in IR
Revised: June 25, 2014 — add PLUS, floating point coprocessor and Sparrowhawk
Revised: July 2, 2024 — add floating FPNEG and FPABS, better hyperlinks.

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