Midterm

22C:122, Fall 1999

1. A Question: Any computer system can be described at 3 levels of abstraction, known by the abbreviations RT, ISP and PMS. Give a one sentence definition of each. (3 points)

2. Background: The Ultimate RISC provides awful support for memory addressing -- self modifying code is required for pointers and indexing. Consider the following idea for extending the ultimate RISC:

   We make no change to the instruction format nor to the fetch execute cycle. We assume address FFFF₁₆ refers to the program counter. We assume that the first 4K words of memory are used for ROM and the last 4K are used for peripheral and coprocessor interface registers. We assume that the machine has a 16 bit word and a 16-register ALU that interprets addresses as follows:

       _______________ _______ _______
      |_______________|_______|_______|
      |1 1 1 1 1 1 1 1|  op   |  reg  |
   
      op =  0 0 0 0 accesses reg directly as src or dst
      op =  0 0 0 1 adds to reg when used as dst
      op =  0 0 1 0 subtract from reg when used as dst
         ...
      op =  1 1 1 1 not used (allows FFFF to reference PC)
   

   The addition we make supports indexed addressing as follows:

       _______ _______________________
      |_______|_______________________|
      |  reg  |          disp         |
   

   If reg is either 0000 or 1111, indexing is disabled and the address given is used with no modification. This allows code to access the ALU, the PC and several thousand low and high memory addresses without using indexing. In all other cases, the reg field selects one of the first 15 registers in the ALU and adds the disp field to the contents of the register to compute the actual memory address.

   At the top level, the following diagram describes the structure of the resulting computer:

       _____________                          data
      | instruction |=======================o====
      |  execution  |     __________        | address
      |     unit    |====| indexing |=====o=|====
      |_____________|    |   unit   |    _|_|_
                         |__________|===| ALU |
                                        |_____|
   

   Part A: There are two alternatives for the communication between the ALU and the indexing unit: One is to have the indexing unit hold private copies of (15 of) the 16 ALU registers, whenever the ALU stores a value in a register, it also sends a copy to the indexing unit.

   In detail, what signals, and traveling in what direction, would you expect on the interface between ALU and indexing unit for this design. (3 points)

   Part B: As part A suggested, there is another design alternative for the data path between the ALU and the indexing unit. Describe this alternative. Design details are not required! (3 points)

   Part C: Give an RT-level diagram of the logic required to implement the indexing unit. For this purpose, ignore the problem you faced in parts A and B, and simply assume a subsystem to which you give the register number, where the response is the value of that register. (3 points)

   Part D: On power-up, the PC register is zero and all RAM and other registers hold random or unknown bit patterns. Give (using reasonable notation) code you would put in ROM to jump to the first location in RAM after the code in ROM finishes loading a program in RAM. (3 points)

   Part E: When you note that, in real programs, roughly 1/2 of all source operands are constants, the Ultimate RISC architecture, even with this indexing unit added, is not very appealing! Suggest a modification to the indexing unit that would allow programs to contain 12-bit immediate constants in source operands. (3 points)

   Part F: Would the extension to allow source operands containing 12-bit immediate constants solve the awkward structure of branch instructions on the Ultimate RISC with this indexing unit added? Explain briefly why or why not. (2 points)