Homework 7

22C:122, Fall 1999

Due Monday Oct 25, 1999, in class

1. Background: Consider the indexing unit for the Ultimate RISC architecture that was the focus of problem 2 in the midterm. (Ignore the discussion of immediate operands!)

   Assume the register file in the ALU has an extra read port, available for use by the indexing unit. The (private or off-bus) interface between the indexing unit and the ALU therefore contains the following 20 signals:

   • from IU to ALU: 4 bits, a register number r
   • from ALU to IU: 16 bits, the contents of R[r]
   In addition, the indexing unit has the following other inputs and outputs:
   • from IEU to IU: 16 bits, the address lines of the bus
   • from IU to others: 16 bits, the indexed address
   Note, specifically, that the indexing unit DOES NOT need or use the read and write signals.

   Part A: Give a clear detailed design for the indexing unit, at the register transfer level.

   Part B: In the paper on the Ultimate RISC, the section titled Programming contains definitions for a group of macros (LDA, STA, ADD, SUB, JMP) that are not appropriate for the machine defined in the exam. Define new macros that provide the user with appropriate tools for programming on this machine. (The presence of the indexing unit actually makes this quite hard unless you back off and assume that the entire program must reside in ROM!)

   Part C: In the paper on the Ultimate RISC, the section titled Programming begins with an example program. Write clearly documented code to carry out this computation, making efficient use of the instruction set from the exam; you may use your macros from part B.

2. Background: To execute an Ultimate RISC program, we must execute 4 memory references per instruction cycle. The natural approach to pipelining such a machine leads to a machine with a 4-stage pipeline, each stage dedicated to performing one of the memory cycles.

   In this problem, make no attempt to solve operand conflicts, hazards or other classical problems with pipelined computers. Assume you may use as many memory ports as you want!

   Part A: Document the function of each stage in this pipeline.

   Part B: Document the contents of all interstage registers in this pipeline.

   Part C: Assuming that you can get 4K by 16 bit single port RAM chips in unlimited quantity, suggest how you would build a memory module appropriate for your pipelined RISC. The material from the end of the notes for Lecture 21 solves half of this problem, but you'll need to propose a way to get separate read and write ports from chips that have only one set of address pins. Note, obviously, you must time-multiplex two addresses on this one set of address pins, so you will have to sacrifice some element of performance to solve this problem!