Background
In the two previous homework assignments, you were asked to study features
of the machine proposed by Berks, Goldstine and Von Neumann in their
Preliminary discussion of the logical design of an electronic computing
instrument and features of the
DEC PDP-8.
There are several huge differences between these machines:
- One had a 40 bit word, the other had a 12 bit word.
- One was to be built from vacuum tubes, the other from silicon.
- Only one was a significant commercial success.
- One had 1-word instructions, the other had half-word instructions.
- The multiply and divide instructions on one were optional.
If you ignore these differences, the machines seem very similar. Both
had program counters, both had a single accumulator, both used a
multiplier-quotient register for the second register needed for
multiply and divide.
Part A:
What major architectural innovations are present in the DEC PDP-8
that were not present in the IAS proposal. There are at least 6;
list at least 4, with a short paragraph for each explaining the
importance of the innovation.
Part B:
One minor innovation in the PDP-8 instruction set was forced by the
very short op-code field of this machine. There is no load-accumulator
instruction.
Assuming all variables are statically allocated and somewhere
in page 0 of memory, explain how the following short code fragment would
be translated to PDP-8 code:
A = B + C
B = C
Part C:
Having done the above exercise, explain the innovation which allows the
load-accumulator instruction to be eliminated at a very modest run-time
cost.