Homework 4

22C:122, Fall 1998

Due Wednesday Sept 23, 1998, in class

1. Background: Consider a pipelined implementation of the Minimal Ultimate RISC where each instruction execution cycle has the following semantics:

   repeat
      M[dst] = tmp;
      tmp = M[src];
      src = M[pc];
      dst = M[pc + 1];
      pc = pc + 2
   forever
   

   Note that the statements in the above semantic description can all be considered to be executed in parallel, so long as the memory is able to support 4 simultaneous access paths; real memory that operates this way can in fact be built, although we usually approximate this behavior with mechanisms that will be discussed later.

   Part A: How does the interpretation of this machine's instruction set differ from that of the Minimal Ultimate RISC discussed in class. Demonstrate your understanding of this difference by writing a program for this machine that computes A = B - C using the ALU discussed in the original presentation of the minimal Ultimate RISC.

   Part B: Outline a register-transfer implementation of this instruction execution unit. Ignore the problem of branch instructions.

   Part C: Re-do your answer to part B to describe how you would add branch instructions, and present a correct pseudocode description of the semantics of the IEU that describes how your branch instructions work.

   Part D: Does this pipelined IEU have any operand delay slots?

   Part E: Does this pipelined IEU have any branch delay slots?