This sequence assumes the following locations are reserved:
; autoincrement locations (memory 8 to 15) SP, .-. / stack pointer, push = pre-increment ; other page zero locations TMP, .-. / temporaryAnd, of course, we assume that SP initially points to a stack somewhere in memory! Given this, here's are the calling, receiving and return sequences:
; calling sequence JMS PROC / AC holds param and result ; receiving sequence PROC, .-. / return address DCA TMP / save argument TAD PROC / get return address DCA I SP / autoincrement push! TAD TMP / get argument ... subroutine body ; return sequence DCA TMP / save result TAD SP / get SP DCA PROC / use PROC as second temp CLA CMA / load -1 in AC TAD SP / computes SP-1 DCA SP / finished decrementing SP TAD I PROC / get return address DCA PROC / save for use TAD TMP / restore result JMP I PROC / return!
____________________________________
| |
| _____________________ |
| | _________________ | |
| | | | | |
| \|_|/ | | |
CLA-------\|/-------o| AND | | | |
CLL-----o|AND| |_____| __________| | |
|___| | | | ________ | |
| \|_|/ | | | | |
CMA-------\|/--------| XOR | __\|_|/__ | | |
CML------|XOR| |_____|| | | | |
|___| | | | Memory | | | |
| | | |_________| | | |
\|/_________\|_|/ | | | | |
RAR------| | \|_|/ | | |
RAL------| shift network | | AND |------| |--|--Memop
Double---|_________________| |_____| | | |
| | | | | | | |
\|/_________\|_|/____\| |/ | | |
| ------a-------- -b- | Cin | | |
Fselect--| 13 bit add/and a op b |-- | | |
|__________________________| | | | |
IAC--------|-----------| |------------- | | |
| | | | | |
\|/ ___\|_|/___ | | |
LINK |_| AC |___________| | | |
| | |_________________| | |
| |_____________________| |
| |
|____________________________________|
In the above, to do an TAD or AND instruction, we set the
CLA, CLL, CMA, CLL, RAR, RAL, Double and IAC lines to 0, set
Fselect to either add or and, depending on the opcode, and set
Memop to allow an operand from memory.
To do a group 1 microcoded operation, we set CLA through IAC lines to the values from the corresponding bits of IR, set Fselect to add, and reset Memop to force the second ALU input to zero.
To do a DCA, we set CLL and CML to zero, we set RAR, RAL and Double to 0, and we set Fselect to and, then set Memop to 0 (forcing the result of the and to 0). Note that CLA, CMA and IAC are irrelevant here.
For all of the above instructions, we clock LINK and AC.
Instruction register:
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
_______________________________________________
| X| | | | X| X| | | X| | | | | | | |
|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|
| op | r| m | offset |
We retain the basic PDP-8 instruction set with no modifications, so that if
all added bits were set to zero, the machine behaves exactly
like a PDP-8. The added bits are marked with X!
New Opcodes:
1000 - OR or memory with R[r]
1001 - SUB subtract memory from R[r]
1010 - XOR exclusive or memory with R[r]
1011 - STA store R[r] in memory
1100 - JSR R[r] gets PC, PC gets EA
1101 - LB load byte from memory
1110 - SB store byte to memory
1111 - ?
Special case for ISZ using r bit:
00100 - behaves as PDP-8 ISZ
00101 - decrement and skip if zero
For the PDP-8 TAD, AND and DCA memory reference instructions, the r bit determines which of two accumulators the operation applies to. For the PDP-8 JSR and JMS instructions, the r bit has no obvious use.
New addressing modes
100 - index mode, EA = offset + R[0]
101 - index mode, EA = offset + R[1]
110 - autoincrement mode EA = ++m[offset]
111 - autodecrement mode EA = m[offset]--
Note that all memory locations in page zero can now be used for both
autoincrement and autodecrement modes!
New bits for group 1 microcoded instructions
_______________________________________________
| 0| 1| 1| 1| | | 0| | | | | | | | | |
|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|
| 0 1 1 1| | CLA | CMA RAR BSW
rd CLL CML RAL IAC
rs SXU
R[rd] is the destination register of the operation
R[rs] is the source register of the operation
SXU if set, top 8 bits of R[rd] cleared after all other ops
The above is only a start. The remainder of the microcoded ops are
not yet defined, nor are the load and store byte operations fully
defined. The machine should normally use word addressing, so perhaps
the load byte and store byte instrucitons use 2-word byte pointers.