22C:060 Computer Organization
Spring 2011

Instructor

Sukumar Ghosh, 201P Maclean Hall, 319-335-0738, ghosh@@cs.uiowa.edu
Class meeting time: 1:05 - 2:20 TTh 218 MLH
Semester hours: 3
Office hours: 11:00-12:00 PM TTh

TA

Sanmitra Bhattacharya, sanmitra-bhattacharya@uiowa.edu,
Office: 101N MLH, 319-335-2839, Office hours 2:30-4:00 PM Mondays and Wednesdays

Textbook

David Patterson and John Hennessy, Computer Organization & Design, 4th Edition Elsevier, 2008.

Course Outline

We will take a top-down approach towards understanding computer organization. We will begin with how high-level language programs are translated into assembly language programs, and how the translated version is interpreted by a basic digital computer. Subsequently, we will discuss how to design the basic building blocks of a digital computer from simpler hardware components.

The software component of the course will introduce assembly language programming of the MIPS processor. It will describe instructions for control-flow, load and store, arithmetic and logical operations, stack handling, various addressing modes and their utility. The hardware components will include logic gates, combinatorial circuits, sequential circuits, ALU design, control unit, memory peripheral interfacing, pipelining, RISC vs. CISC, performance issues. For the purpose of illustration, we will use examples from the MIPS processor.

Tests and assignments

There will be 6 homeworks, two quizzes and two examinations. The homeworks will account for 30% of the final grade. The quizzes will account for 10% of the final grade, and the tests will be worth 60% (midterm 25% and final 35%) of the final gradeThe tests will be scheduled as follows:

Midterm Exam: Tuesday, March 1, 2011 (in class)
Final Exam: Tuesday, May 10, 2011, 218 MLH, 7:30-9:30 AM

Letter grades will be assigned roughly as follows:

A+ = 95-100     B+ = 80-84      C+ = 65-69      D+ = 50-54      F = 0-39
A  = 90-94      B  = 75-79      C  = 60-64      D  = 45-49
A- = 85-89      B- = 70-74      C- = 55-59      D- = 40-44

The instructor reserves the right to make minor modifications in the grading scale.

Schedule of events

Homework

Homework 1 Assigned Feb 1, due Feb 8
Homework 2 Assigned Feb 15, due Feb 22
Homework 3 Assigned March 22, due March 29
Homework 4 Assigned March 31, due April 7
Homework 5 Assigned April 14, due April 21
Homework 6 Assigned April 26, due May 3

THE SPIM SIMULATOR

Information about downloading and different versions
MIPS Assembly Language Handout
A SPIM Tutorial
Sample Assembly Language Program

Lecture Notes

January 18, 2011
Lecture 1. Introduction to Computer Organization
January 20, 2011
Lecture 2. High-level vs Assembly Language Programming
January 25, 2011
Lecture 3. MIPS instruction formats
January 27, 2011
Lecture 4. MIPS assembly language programming
February 1, 2011
Lecture 5. Branch, jump and subroutine linking
Homework 1 assigned.
February 3, 2011
Lecture 6. Subroutine linking
February 8, 2011
Lecture 7. Recursive procedure call
February 10, 2011
Lecture 8. Instruction Set -- Exception handling
February 15, 2011
Lecture 9. Exception Handling continued. Introduction to Logic Design
For Logic Design, read Appendix C from the CD at the end of the book.
Homework 2 assigned.
February 17, 2011
Lecture 10. Boolean Algebra
Read Appendix C from the CD at the end of the book.
A copy of this appendix is posted on ICON.
February 22, 2011
Lecture 11. The building blocks: adder, decoder, encoder , multiplexor, demultiplexor
Read Appendix C from the CD at the end of the book.
February 24, 2011
Lecture 12. A 1-bit Arithmetic Logic Unit (ALU)
March 3, 2011
Lecture 13. 32-bit adder -- Carry look-ahead
Review for Exam 1.
March 8, 2011
Lecture 14. Floating point representation
March 10, 2011
Lecture 15. Floating Point instructions in MIPS. Introduction to Flip-flop, registers, counters
March 22, 2011
Lecture 16. Multiplication and Division
Read the material from Chapter 3.
Homework 3 assigned.
March 24, 2011
Lecture 17. Register file & Memory
March 29, 2011
Lecture 18. Inside RAM and ROM
March 31, 2011
Lecture 19. Cache Memory
Homework 4 assigned.
April 5, 2011
Lecture 20. Cache Memory (continued)
April 7, 2011
Lecture 21. 1-cycle implementation of MIPS
April 12, 2011
Lecture 22. 1-cycle MIPS processor (continued)
April 14, 2011
Lecture 23. Multicycle implementation of MIPS
Homework 5 assigned.
April 19, 2011
Lecture 24. Pipelined MIPS
April 21, 2011
Lecture 25. Input Output Operations
Polled I/O
interrupt-driven I/O
April 26, 2011
Lecture 26. Intel Pentium
Homework 6 assigned.
April 28, 2011
Lecture 27. Virtual Memory
May 03, 2011
Lecture 28. Virtual Memory
May 05, 2011
Lecture 29. Multi-core processors
What is GPGPU?

Miscellaneous Topics

Atanasoff Berry Computer