22C:160, 55:132 High-Performance Computer Architecture
Spring 2006

Instructor

Sukumar Ghosh, 201P Maclean Hall, 319-335-0738, ghosh@cs.uiowa.edu
Class meeting time: TTh 3:55 - 5:10 PM, 4030 SC
Office hours: TTh 10:30 AM-12:00 PM

Teaching Assistant

Chen Zhang, 201N MLH, chenzhan@cs.uiowa.edu
Office hours 2-5 Wednesdays, or by appointment.

Textbook

Patterson D.A. and Hennessy J.H. ``Computer Organization and Design: The Hardware Software Interface'' (3rd edition) Elsevier 2005. In addition, readings will be assigned from a list of papers.

Prerequisites

Basic knowledge of Digital Logic, Computer Organization, Assembly Language Programming, and elementary systems software concepts like Virtual Memory, Multiprogramming etc.

Tests and Assignments

There will be two examinations.
Exam 1 (35%) : March 2, 6-8 PM, 140 SH
Exam 2 (35%) : May 11, 7:30-9:30 AM, 4030 SC

There will be five home assignments, which will account for the remaining 30% of the grades.

Letter grade distribution
A+ = 95-100     B+ = 80-84     C+ = 65-69     D+ = 50-54    F = 0-39
A  = 90-94      B  = 75-79     C  = 60-64     D  = 45-49
A- = 85-89      B- = 70-74     C- = 55-59     D- = 40-44

The instructor reserves the right to make minor modifications in the above grading scale.



Course Outline (tentative)

Home assignments

Homework 1
Solution to homework 1 (by Chen Zhang)
Homework 2
Solution to homework 2 (by Chen Zhang)
(The last line for question 1 part a should be "Reg[IR[20:16]]" instead of "Reg[IR[15:11]]")
Homework 3
Solution to homework 3 (by Chen Zhang)
Homework 4
Solution to homework 4 (by Chen Zhang)
Homework 5
Solution to homework 5 (by Chen Zhang)

Lecture notes

January 17, 2006
Lecture 1. Introduction: Important Architectural Issues
Read Chapter 1. Refresh your background
January 19, 2006
Lecture 2. Instruction Set Design: Understanding the MIPS Processor
Read Chapter 2.
January 24, 2006
Lecture 3. Understanding the MIPS Processor (continued)
Read Chapter 2.
January 26, 2006
Lecture 4. Designing the MIPS Processor
Read Chapter 5.
Homework 1 assigned.
January 31, 2006
Lecture 5. From single-cycle to multi-cycle MIPS
Read Chapter 5.
February 2, 2006
Lecture 6. Designing the control unit of multi-cycle MIPS
Read Chapter 5. Also read Appendix C on the CD at the end of the textbook
February 6, 2006
Lecture 7. The IA-32 Architecture
Read Section 2.16. Also visit the Intel page
February 9, 2006
Lecture 8. Introduction to Pipelining
Read Chapter 6.
February 14, 2006
Lecture 9. Dealing with branches in pipelined processors
Read Chapter 6.
February 14, 2006
Lecture 10. Handling exceptions and floating point operations
Read Chapter 6.
Homework 2 assigned.
February 21, 2006
Lecture 11. The Memory Hierarchy
Read Chapter 7.
February 23, 2006
Lecture 12. Cache memory
Read Chapter 7.
February 28, 2006
Lecture 13. Cache memory (continued)
Read Chapter 7.
March 2, 2006
Lecture 14. Exam review and case study
Exam 1 today 6-8 PM 140 SH.
March 7, 2006
Lecture 15. Virtual memory
Read Section 7.4.
March 9, 2006
Lecture 15. Implementing Virtual memory
Read Section 7.5.
Homework 3 will be posted tomorrow - it is due 3/23
March 21, 2006
Lecture 16. Dynamic pipeline scheduling and dynamic branch prediction
Read Sections 6.9 and 6.6.
Midterm exam has been graded
March 23, 2006
Lecture 17. Dynamic branch prediction, Instruction Level Parallelism
Read Section 6.9
March 28, 2006
Lecture 18. More about Instruction Level Parallelism & Review of Pentium micro-architecture
Read this article
Read Section 6.10, 6.11
March 30, 2006
Lecture 19. Computer Arithmetic
Read Appendix B
April 4, 2006
Lecture 20. Floating point numbers and algorithms
Read Chapter 4
April 6, 2006
Lecture 21. Classification of architectures: Introduction to multiprocessing
Read Chapter 9 (9.1-9.3 on the CD)
Homework 4 assigned.
April 11, 2006
Lecture 22. Multiprocessing: Interconnection Networks and Performance Issues
Read Chapter 9 (from the CD)
April 13, 2006
Lecture 23. Storage and Input-Output
Read Chapter 8
April 18, 2006
Lecture 24. Case Study: Transmeta's Crusoe Processor
Notes
April 20, 2006
Lecture 25. Multiprocessor Cache Coherence
MESI protocol
Homework 5 will be assigned tomorrow, due 4/27/06
April 25, 2006
Lecture 26. Multiprocessor Synchronization
Read Chapter 9 from CD
April 27, 2006
Lecture 27. Multiprocessor Synchronization (continued)
Read Chapter 9 from CD
May 2, 2006
Lecture 28. Benchmarking and performance issues
May 4, 2006
Lecture 29. Review

Additional Resources