Andrew Reynolds

I am a Research Scientist at the University of Iowa. My research focus is on various aspects of Satisfiability Modulo Theories, including quantified formulas, decision procedures, and proof checking. I am the primary developer of the module for handling quantified formulas in the SMT solver CVC4. My current focus is developing new techniques for handling quantified formulas within SMT solvers, including heuristic E-matching, finite model finding, model-based instantiation, methods for automating proofs by induction, and approaches for synthesis conjectures.


Conference Papers

Workshop Papers

Journal Papers

Technical Reports




My work in CVC4 has been entered in the following competitions:

Program Committee Experience

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